Asynchronous Transfer Mode (ATM) is a packet oriented technology which permits continuous bit rate signals carrying one or more of voice, video, and data, to be conveyed across a broadband network within packets. ATM is suitable for the transport of bursty traffic such as data, as well as accommodating constant or continuous bit rate signals. In delivering continuous bit rate traffic (e.g., T1, DS3 signals) in a broadband network, a service clock controlling a destination node buffer must operate at a frequency precisely matched to that of a service clock at a source node in order to avoid buffer overflow or underflow and resulting loss of data.
One problem with synchronizing the service clock at the destination node with the service clock at the source node is "cell jitter" that is inherent in the use of an ATM network. Cell jitter is the random delay and aperiodic arrival of cells at a destination node. In other words, cell jitter means that all of the cells or packets that travel between a source node and a destination node do not take the same amount of time to travel through the ATM network. Thus, it is difficult to use the cell arrival times to directly synchronize the frequency of the service clock at the destination node with the service clock at the source node.
Numerous schemes have been proposed to provide a mechanism for synchronizing the service clocks of source and destination nodes in the presence of cell jitter. This is also referred to as "service clock recovery." Descriptions of many of these schemes are provided in Fleischer et al. U.S. Pat. No. 5,260,978 (the '978 Patent). The '978 Patent incorporated by reference. Perhaps the most elegant and widely accepted of the service clock recovery schemes is known as synchronous residual time stamp (SRTS or RTS) encoding. SRTS encoding is specified, for example, in T1.630, Annex A for delivering T1 service over an ATM network.
The '978 Patent describes one embodiment of SRTS encoding. A free running four bit counter is used at the source node to count cycles of a common network clock. At the end of every residual time stamp (RTS) time period formed by 3008 service clock cycles (i.e., eight cells of forty-seven bytes of data each), the current four bit count of the four bit counter is transmitted in the ATM adaptation layer (AAL1) by using one bit in every other byte of the AAL1 for eight cells. It should be noted that the AAL1 is the overhead byte which accompanies the forty-seven bytes of data to constitute the forty-eight-byte payload of an ATM cell. The ATM cell also includes five additional bytes of header. The four-bit SRTS provides sufficient information for unambiguously representing the number of network clock cycles within a predetermined range.
The clock recovery at the destination node according to the '978 Patent involves determining from the received RTSs the number of network clock cycles in each RTS period, and generating a pulse signal from the network clock in which the period of the pulse equals the determined number of network clock cycles in the corresponding RTS period. The pulse frequency is then multiplied by 3008 in order to recover the source node service clock.
While the clock recovery mechanism of the '978 Patent might be suitable for recovering the source node service clock, it is neither the only recovery mechanism possible, nor necessarily the most optimal mechanism for recovering the source node service clock.
U.S. Pat. No. 5,608,731, entitled Closed Loop Clock Recovery for Synchronous Residual Time Stamp (the '731 Patent) describes another service clock recovery technique using SRTS. The '731 Patent describes an apparatus with a digitally controlled oscillator at the destination node. A local RTS-related value is generated at the destination node based on the output of the digitally controlled oscillator. RTS values from incoming data packets are compared to the local RTS-related values generated at the destination node. This provides a feedback error or control signal. The control signal is used to adjust the digitally controlled oscillator at the destination node. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa. Unfortunately, the complex circuitry used in this closed loop must be replicated for each port at the destination node. Further, this closed loop solution suffers from problems common to closed loop control circuits.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved circuit and method for service clock recovery.